PCIe PHY - PCI Express PHY - SERDES Based Products -
Phylinks technology inside!
Our SERDES based IP product line currently consists of General
Purpose SERDES, SATA and PCIe PHY (PCI-Express
PHY) cores. We offer our
customers PHY, Link and Driver Software cores. The Innovative
Products are based on the
Phylinks High Speed Serial technology.
Phylinks PHY technology is optimized for
minimum area, low power and Design For Test and Manufacturing,
attributes that are ideal in the development of high performance
communications, PC, mass storage, optical and server
applications.
Innovative's SATA
PHY and PCIe (PCI Express) PHY are based on Phylinks
SerDes
PHY
technology.
Phylinks is a member
of PCI-SIG as well as
SATA-IO.
Two
Important Differentiating Features of the Phylinks Technology
Besides the usual
features that the SOC designer expects in today's commercially
available PHY, the Phylinks technology has the following
advantages
-
DFT features were
considered as primary goals when developing the SERDES
PHY Architecture. This was definitely not an after thought! DFT
is considered very crucial to testing SOCs during the
initial debug phase, the yield analysis phase and during
production testing especially for mixed-signal blocks. BIST
Logic allows self-testing at high speed of the Analog and
the Digital SerDes. Extensive and Configuration Capabilities
are designed in the PHY.
-
Phylinks' Serial
Technology strikes the right balance between the digital and
analog functions to optimize the PHY design. This crucial
balance, when carefully analyzed and well implemented, can
result in small area, reduced porting time - from one
process to another and in this case lower power PHY.
SerDes
The SERDES IP core provides a complete and flexible PHY layer
solution for low power, high speed serial links, from 250Mbps to
6.25Gbps, for use in designing SOCs,
the SERDES can be configured for by 1,4,8 or 16, providing
scalability to meet the number of the desired lanes. I The
PHY consists of the serializer, transmitter, receiver,
deserializer and Clock and Data Recovery (CDR). A separate
reference block - the reference cell - contains the Clock
Circuit , Band Gap and Bias Circuits. The PHY targets backplane, XAUI, Fibre
Channel, InfiniBand, PCIe and SATA applications.
PCIe - PCI Express PHY
ISI-820: The PCIe PCI Express PHY IP provides a complete PHY layer
solution for the PCIe. The Macrocell integrates the SerDes and
PIPE Interface Logic. It can be implemented in Standard Digital
CMOS technology with a single 1.2V supply.
Innovative works with several partners to provide the Controller together with
its PHY Macrocell thus providing easy to integrate PCIe
solution. The PHY together with the controller
interface to the PCIe bus on one side and to the Application
Bus on the other side.
The following are Our PCIe products. In order
to view the datasheets, please complete the
Information Request Form
(in the more information box on the right).
 PRODUCTS |
NUMBER |
PROCESS |
| General
Purpose SERDES |
|
.18, .13, .09 |
|
PCIe
PCI Express PHY |
|
.18, .13, .09 |
| PCIe
Link Controller |
Third
Party |
RTL |
| |
|
|
